Hardware & Semiconductor Topics
14 topics
- Hardware & Semiconductor
FPGA (Field Programmable Gate Array)
A reconfigurable semiconductor that reconfigures its internal circuits via a bitstream even after manufacturing — covering the internal structure of LUTs, flip-flops, interconnect, BRAM, and DSP, the RTL->synthesis->place-and-route->timing-closure->bitstream design flow, SRAM/flash/antifuse types and comparison with CPU/GPU/ASIC, cases such as data-center AI inference, HFT, 5G, and cloud FPGA, and latest trends including HLS, partial reconfiguration, adaptive computing (ACAP), chiplet, eFPGA, and CXL, with adoption strategy, security, and TCO organized in depth from a professional-engineer perspective.
- Hardware & Semiconductor
NAND Flash-Based SSD (FTL, Wear Leveling, Garbage Collection)
A semiconductor storage device that hides NAND flash constraints — no in-place overwrite, block-granular erase, finite lifetime — behind the FTL to present a block device: structure, FTL operation, cell types (SLC~QLC), over-provisioning, write amplification (WAF), and host-cooperative architectures such as ZNS and computational storage.
- Hardware & Semiconductor
UALink-Based AI Accelerator Scale-Up Fabric
An essay-style study note on the UALink scale-up fabric for low-latency, high-bandwidth, memory-semantic communication among AI accelerators. Covers the UPLI, transaction, data-link and physical layers; address translation and flow control; collective-communication topologies; role comparisons with NVLink, CXL and Ethernet; a hypothetical LLM-training pod; UALink 2.0 in-network compute, chiplet integration and manageability; and professional-engineer considerations for interoperability, security and TCO.
- Hardware & Semiconductor
DPU (Data Processing Unit) and SmartNIC
An essay-format overview of the DPU/SmartNIC, a data-movement-centric programmable processor that offloads, accelerates, and isolates infrastructure processing (networking, storage, security) from the CPU: its definition, architecture, offload types, comparison of SmartNIC approaches, recent trends, and professional-engineer considerations.
- Hardware & Semiconductor
Silicon Photonics and Optical Interconnects
A technology that reuses the CMOS process to integrate optical devices onto silicon, moving data with light instead of electrons—covering core devices (laser, modulator, waveguide, detector) and WDM, the architectural evolution from pluggable to LPO to CPO (co-packaged optics), the distance/power break-even versus electrical wiring and the thermal/reliability trade-offs, and recent trends as core infrastructure for AI datacenter interconnects.
- Hardware & Semiconductor
The Semiconductor Industry (Memory, Non-Memory, Value Chain)
A comparison of memory and non-memory semiconductors, the design-manufacturing-packaging value chain, and strategies such as fostering fabless companies to grow the non-memory sector.
- Hardware & Semiconductor
NPU (Neural Processing Unit)
This essay covers, in a professional-engineer answer format, the architecture, dataflow, performance metrics, comparison with CPUs and GPUs, and recent trends of the NPU, an AI-dedicated accelerator that specializes and accelerates the multiply-accumulate operations of neural networks through systolic arrays, low-precision arithmetic, and data reuse.
- Hardware & Semiconductor
Neuromorphic Chip
A brain-inspired semiconductor that mimics the brain's neurons and synapses to integrate computation and memory and operate via spikes, enabling low-power edge AI.
- Hardware & Semiconductor
Qubit
The qubit as a unit of quantum information that represents 2^n states simultaneously via superposition and entanglement of 0 and 1: its principles, implementation, decoherence, and cryptographic threats.
- Hardware & Semiconductor
Processing-in-Memory (PIM)
A data-centric semiconductor architecture that integrates compute units inside memory (DRAM) to perform computation in place without moving data to the processor, mitigating the memory wall of the von Neumann architecture and the power cost of data movement. An essay-style overview of the operating principle exploiting bank-level parallelism, types by compute-unit placement (bank, logic die, PNM) and by circuit method (digital, analog crossbar), the offloading execution flow, per-memory application cases such as HBM-PIM, GDDR6-AiM, and CXL-PNM and comparison with GPUs and neuromorphic computing, and Professional-Engineer-level considerations such as selective-offloading strategy, area/heat/precision trade-offs, and the standards (JEDEC, CXL) ecosystem.
- Hardware & Semiconductor
Chiplet Architecture and Heterogeneous Integration
An approach that, instead of one large monolithic die, heterogeneously integrates smaller dies divided by function and process node into a single package using the UCIe standard D2D interconnect and 2.5D/3D packaging—a semiconductor design and packaging architecture that overcomes the cost, yield, and reticle limits of advanced process nodes and forms the foundation for AI chips and HBM integration.
- Hardware & Semiconductor
CXL (Compute Express Link) High-Speed Interconnect
An open standard that layers cache coherence and memory semantics on the PCIe physical layer to connect CPUs, accelerators, and memory with low latency—covering the three layers CXL.io/cache/mem, Type 1/2/3 devices, and resolving the memory wall and idle waste in AI and data centers through memory expansion, pooling, and sharing.
- Hardware & Semiconductor
RISC-V (Open Instruction Set Architecture)
An open, royalty-free instruction set architecture originating at UC Berkeley. By layering standard and custom extensions modularly onto a small, fixed base integer ISA (RV32I/RV64I), it enables freedom from licensing lock-in and domain-specific computing, spreading from embedded systems to AI and servers.
- Hardware & Semiconductor
High Bandwidth Memory (HBM)
Memory that achieves ultra-high bandwidth and low power by 3D-stacking DRAM with TSV — resolving the memory bottleneck (Memory Wall) in AI and HPC.