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#UCIe#칩렛#다이 간 인터커넥트#이종집적#어드밴스드 패키징
Last updated · 2026-10-31

UCIe (Universal Chiplet Interconnect Express) Standard

1. Overview

Definition: UCIe (Universal Chiplet Interconnect Express) is an open die-to-die interconnect standard for connecting different dies within a single package. It defines a three-layer structure of physical layer, die-to-die adapter, and protocol layer, along with standard and advanced packaging options, so that chiplets from different processes and vendors can be assembled into a single system.

The semiconductor industry long raised performance through a monolithic SoC strategy that integrated every function onto a single silicon die. As Moore's Law hit physical and economic limits, however, this strategy ran into two walls. The first is the wall of yield. As die area grows, the probability that it contains at least one defect increases exponentially, so a large die approaching the reticle limit (about 800mm²) suffers a steep drop in production yield. The second is the wall of process cost. As wafer prices for leading-edge processes below 3nm have soared, manufacturing even blocks with little benefit from scaling—such as I/O or analog—on the latest process is economically inefficient.

The solution that emerged is the chiplet architecture. A large SoC is divided into smaller dies by functional unit—compute, memory, I/O—each manufactured separately on its optimal process, then reintegrated into one package (heterogeneous integration). Yet for a chiplet strategy to spread into an industry ecosystem, the interconnect joining die to die must be standardized. Otherwise, as with AMD's Infinity Fabric or Intel's AIB, each vendor uses a proprietary spec, chiplets cannot be freely mixed, and the open ecosystem of a "chiplet marketplace" cannot form.

UCIe was launched to fill exactly this gap, when major companies including Intel, AMD, Arm, TSMC, Samsung, ASE, Google Cloud, Meta, Microsoft, and Qualcomm formed a consortium in March 2022. Just as PCIe and CXL became the de facto standards at the board level (chip-to-chip), UCIe aims to be the standard at the package level (die-to-die). The core value of UCIe lies not in mere high-speed transfer but in providing the foundation of an open ecosystem where chiplets from different processes and different vendors interoperate.

Compressing this background, UCIe can be likened to "the USB and PCIe inside a package." Just as peripherals once had different dedicated connectors and then converged on USB, triggering explosive ecosystem growth, converging die-to-die connections on UCIe lets design firms focus on functional innovation rather than reinventing the interconnect each time. Especially where access to leading-edge processes is concentrated in a few foundries, chiplet reuse and a standard interconnect become practical levers for cutting design cost and time-to-market (TTM).

2. UCIe Layered Structure and Core Components

Like PCIe, UCIe adopts a layered architecture. By clearly separating each layer, a lower physical layer can be reused even when the upper protocol changes, and conversely the upper protocol is unaffected when the physical layer (packaging) changes—achieving a separation of concerns. The overall structure is as follows.

graph TB
  subgraph Die_A["Chiplet A"]
    PA["Protocol Layer(PCIe/CXL/Streaming)"]
    AA["Die-to-Die Adapter(CRC·Retry·Link State)"]
    PHA["Physical Layer(Logical PHY·Electrical AFE)"]
  end
  subgraph Die_B["Chiplet B"]
    PHB["Physical Layer(Logical PHY·Electrical AFE)"]
    AB["Die-to-Die Adapter(CRC·Retry·Link State)"]
    PB["Protocol Layer(PCIe/CXL/Streaming)"]
  end
  PA -->|FDI| AA
  AA -->|RDI| PHA
  PHA <-->|"Die-to-Die Physical Link(Mainband+Sideband)"| PHB
  PHB -->|RDI| AB
  AB -->|FDI| PB

A. Protocol Layer. The topmost layer, it defines the meaning of the data to be transmitted. UCIe supports three mappings. The widely used PCIe and the cache-coherent CXL can be carried as-is, enabling reuse of existing software and IP assets. It also provides a Streaming (Raw) mode that carries raw data without being bound to a specific protocol, accommodating custom protocols or dedicated traffic between AI accelerators. Leaving the protocol choices broad reflects a design intent to cover applications ranging from general-purpose PCs to datacenter accelerators under one standard.

B. Die-to-Die Adapter. Sitting between the protocol layer and the physical layer, it is the core block responsible for link reliability. It attaches a CRC to detect errors, performs retry/replay on error, and handles link state management and power management. It also performs parameter negotiation, in which the two dies exchange their capabilities (supported speed, width, protocols), and arbitration when multiple protocols share one link. Because the adapter connects to the upper side via FDI (Flit-aware Die-to-Die Interface) and the lower side via RDI (Raw Die-to-Die Interface), it can be reused as-is even when the physical-layer configuration differs.

C. Physical Layer. The lowest layer handling actual electrical signals, it is further divided into a Logical PHY and an electrical AFE (Analog Front-End). The Logical PHY performs link initialization and training, lane repair, and sideband management, while the electrical AFE handles the transmit/receive drivers and clock forwarding. A UCIe physical link consists of a mainband that carries actual data and a low-speed sideband dedicated to parameter exchange, register access, and management. Because the sideband is separated, the mainband can focus purely on data transfer, raising bandwidth efficiency.

Layer Core function Upper/lower interface Analogy (PCIe)
Protocol layer PCIe/CXL/Streaming mapping, defines data meaning Upper: device IP Transaction layer
Die-to-die adapter CRC·retry, link state, parameter negotiation, arbitration FDI(up)·RDI(down) Data link layer
Physical layer Link training, electrical signals, clock forwarding, sideband RDI(up) Physical layer

D. Significance of the standard interfaces (FDI·RDI). The FDI and RDI that UCIe defines as layer boundaries are not mere internal signal bundles but key enablers of IP modularity. FDI (Flit-aware Die-to-Die Interface) is the flit-aware interface between the protocol layer and the adapter, while RDI (Raw Die-to-Die Interface) is the interface between the adapter and the physical layer. Because these boundaries are standardized, PHY IP and protocol IP made by different suppliers can be combined like building blocks. For example, a design house can place its own adapter and protocol blocks on top of a proven UCIe PHY provided by a foundry. This lays a basis for the chiplet ecosystem to be reused and traded not only at the die level but also at the IP-block level.

3. Packaging Options and Physical Implementation

The decisive reason UCIe can claim to be "Universal" is that it supports two packaging options with very different cost and performance requirements on top of the same protocol and adapter. The designer chooses the packaging to match the application's bandwidth, power, and cost targets while keeping the upper layers intact. A typical link-setup flow is as follows.

flowchart LR
  S["Chiplet design start"] --> C{"Bandwidth/cost target?"}
  C -->|"Cost·distance first"| STD["Standard Package(2D organic substrate)"]
  C -->|"Performance·density first"| ADV["Advanced Package(2.5D/3D interposer)"]
  STD --> T["Link training·parameter negotiation(sideband)"]
  ADV --> T
  T --> O["Mainband data transfer begins"]
  O --> M["Runtime error detection·retry·power mgmt"]

A. Standard Package. Dies are placed in 2D on a conventional organic substrate and joined by routing. The bump pitch is relatively coarse at about 100–130µm, but it can connect over a comparatively long distance of up to about 25mm and has low manufacturing cost. The reported power efficiency is about 0.5pJ/bit. It suits cost-sensitive applications or those needing long-distance connections.

B. Advanced Package. It uses 2.5D/3D integration such as a silicon interposer or silicon bridge (e.g., EMIB). Narrowing the bump pitch to about 25–55µm lets far more wires pass through a unit area, so the areal bandwidth density is several to tens of times higher than the standard package. In return, the connection distance is short at about 2mm and manufacturing cost is high. Power efficiency is better at about 0.25pJ/bit. It is used in applications demanding extreme bandwidth, such as HBM integration or AI accelerators.

An important principle here is that bandwidth density is inversely proportional to the square of the bump pitch. Reducing the pitch by a factor of x increases the number of wires per unit area by x², so areal bandwidth rises as 1/x². For example, halving the pitch from 100µm to 50µm theoretically quadruples the areal bandwidth density. This is why leading-edge AI chips choose advanced packaging despite the cost. In practice, the areal bandwidth density of advanced packages is reported to reach the range of several hundred to 1,000 GB/s/mm².

Power-efficiency figures also bear directly on design decisions. The difference between 0.5pJ/bit and 0.25pJ/bit is 2× per bit, which in an AI accelerator carrying tens of TB/s of die-to-die traffic is amplified into a difference of several watts (W) in total package power. That is, advanced packaging lowers not only density but also "the energy to move one bit," easing the power bottleneck of modern accelerators where data movement consumes more power than computation. Conversely, the standard package, though its per-bit energy is somewhat higher, can place many chiplets over a wide area on a cheap organic substrate, giving it an advantage in integration density per cost. In this way, UCIe is designed to accommodate both the opposing goals of "performance/power optimization" and "cost/area optimization" on a single protocol.

Category Standard package Advanced package
Integration method 2D organic substrate 2.5D/3D interposer·bridge
Bump pitch 100–130µm 25–55µm
Reach ~25mm (long) ~2mm (short)
Power efficiency ~0.5pJ/bit ~0.25pJ/bit
Bandwidth density relatively low several to tens of times higher
Cost low high

Latency targets under 2ns for both packages, designed so die-to-die communication appears as if within the same die. The data rate supported up to 32GT/s per lane in the initial 1.0/1.1 specs.

4. Comparison with Similar Interconnects

To understand UCIe's position, it must be compared with interconnects of different connection scope. UCIe, CXL, and NVLink are often placed side by side, but they are complementary technologies at different layers rather than competitors. The root cause of the differences lies in the connection scope—"what connects to what."

CXL is a chip-to-chip (outside-package) cache-coherent interconnect that operates on top of the PCIe physical layer, binding CPU, memory, and accelerators coherently at the board level. UCIe, by contrast, is a shorter, denser connection that joins die to die inside a package. Interestingly, UCIe can carry CXL as-is at the protocol layer. That is, like "CXL over UCIe," UCIe can serve as the die-to-die physical carrier for CXL, so the two combine vertically. NVLink and UALink are accelerator fabrics that scale up multiple accelerators to the node/rack level, covering a far broader scope than UCIe.

Technology Connection scope Main use Coherency Relation to UCIe
UCIe Die-to-die (in-package) Chiplet assembly Protocol-dependent This standard
CXL Chip-to-chip (board) Memory·accelerator pooling Yes Mappable onto UCIe
PCIe Chip/board-to-board General I/O No Mappable onto UCIe
UALink/NVLink Node·rack (scale-up) Accelerator fabric Yes Upper scaling layer
AIB/BoW Die-to-die Chiplet (proprietary·other std) No Competing·alternative std

Even before UCIe there were die-to-die specs such as Intel's AIB and OCP's BoW (Bunch of Wires). But these leaned toward specific vendors or ecosystems, limiting universal interoperability. With PCIe/CXL compatibility and broad industry participation as weapons, UCIe is preempting the position of the de facto standard for die-to-die interconnect—this is its practical implication.

5. Deep Dive: Standard Evolution and the Chiplet Marketplace

UCIe is evolving rapidly. The key specification milestones are summarized below.

Version Release Key content
1.0 March 2022 First spec, 3 layers·standard/advanced package, up to 32GT/s per lane
1.1 2023 Reinforced reliability use cases (automotive, etc.), improved error handling
2.0 August 2024 Added manageability (DFx)·system architecture·3D packaging support
3.0 August 2025 (reported) Planar rate doubled to 64GT/s, 3D fine-pitch expansion

After the 1.0 spec in March 2022 and through 1.1, the UCIe 2.0 specification was released in August 2024. The core additions of 2.0 are ① manageability features, standardizing per-die state monitoring, debug, and test (DFx) to ease the operation and diagnosis of complex systems made of many chiplets; ② reinforced system architecture definitions; and ③ added 3D packaging support, further raising bandwidth density and power efficiency in structures that stack dies vertically. 2.0 maintains backward compatibility with 1.0 and 1.1.

Subsequently, the UCIe 3.0 specification is reported to have been released in August 2025. According to reports, 3.0 doubles the planar data rate from 2.0's 32GT/s to 64GT/s and includes a direction of narrowing bump pitch to a few µm or below in its 3D variant (though the detailed figures require confirmation against the official consortium specification). This 2× cadence of bandwidth doubling shows a development pattern similar to PCIe's trajectory of doubling the transfer rate each generation.

The ultimate goal of standardization is realizing the chiplet marketplace. Once UCIe unifies the physical and protocol layers, an ecosystem becomes possible in which one procures company A's compute chiplet, company B's I/O chiplet, and company C's HBM like parts and assembles them into a single package. This is a paradigm shift turning chip design from "monolithic integration" to "Lego-like assembly." The representative application areas are as follows.

  • AI/HPC accelerators: Integrating a compute die (leading-edge process) + HBM + I/O die in an advanced package maximizes memory bandwidth and compute density simultaneously. Since data-movement energy governs total power, a low-pJ/bit link is decisive.
  • Datacenter CPU/server SoCs: A mixed strategy separates I/O and memory controllers into older-process chiplets to lower cost, while manufacturing only the compute cores on a leading-edge process.
  • Autonomous-driving/automotive SoCs: In an area where functional safety (ASIL) and scalability matter, the reliability features reinforced in 1.1 and chiplet reuse efficiently compose product lineups of various grades.

Korea's Samsung and SK hynix are also responding to this trend based on consortium participation and advanced-packaging capabilities (e.g., Samsung I-Cube, SK hynix HBM).

6. Considerations and Implications

UCIe is a technology that standardizes die-to-die connection, but its adoption is ultimately decided together with the cost, yield, power, and ecosystem maturity of the entire chiplet strategy. From a professional engineer's perspective, the following must be judged comprehensively when reviewing UCIe adoption and chiplet strategy.

  • Application strategy (packaging choice). Advanced packaging is not the answer for every application. The key is differentiated application—choosing the advanced package for AI accelerators and HBM integration where bandwidth is vital, and the standard package for general-purpose SoCs where cost and long-distance connection matter. A strength of UCIe is that this choice can be made relatively freely because it shares the upper layers.

  • Trade-off (KGD and test). The success of a chiplet strategy hinges on securing Known Good Dies (KGD). Because integrating multiple chiplets and finding even one defective discards the whole package, the cost structure is governed by per-die testing before integration and by post-integration diagnosis through the manageability/DFx features that UCIe 2.0 reinforced. Assembly yield and repair strategy must be designed together.

  • Outlook (ecosystem dependency and standard maturity). Even an open standard needs compliance certification and a mature IP ecosystem for real interoperability. Demonstrated cases of mixing multi-vendor chiplets are still limited, so chiplet partitioning within a single vendor is likely to remain mainstream for now. Mid-to-long-term investment decisions must consider backward compatibility across standard versions and the roadmap (2.0→3.0).

  • Related technologies (security·thermal·design methodology). A die-to-die link can become a new attack surface, so hardware-security design such as integrity and authentication for the sideband/management channels must proceed in parallel. Also, integrating dies in a tight space sharply increases thermal density, so thermal design (TIM·cooling) constrains performance, and an SoC architecture design methodology premised on chiplet partitioning (partitioning·floorplanning) and EDA-tool support are essential prerequisites.

  • Verification·compliance system. The premise of multi-vendor interoperability is rigorous conformance testing. Planning from the early design stage a compliance program that cross-verifies electrical specs (eye diagram·jitter) and protocol behavior, together with test access (sideband-based DFx) to secure KGD before integration, can reduce rework cost at the back-end stage.

  • Domestic industry perspective. For domestic companies competitive in memory (HBM) and advanced packaging, UCIe standardization is both an opportunity and a challenge. Securing standard leadership, internalizing packaging processes, and building a vertical collaboration framework across foundry-packaging-design emerge as strategic tasks.

References

In one line: UCIe is an open die-to-die interconnect standard that, through a three-layer structure of physical layer, die-to-die adapter, and protocol layer plus standard/advanced packaging, lets chiplets from different processes and vendors interoperate and be assembled into a single package.