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#MRAM#PCM#ReRAM#SCM#비휘발성메모리
Last updated · 2026-10-10

Emerging Non-Volatile Memory (Emerging NVM) and Storage Class Memory (SCM)

1. Overview

A. Definition

Emerging Non-Volatile Memory is a family of novel-device memories that retain data even when power is removed while aiming for access speeds close to DRAM and byte-addressability, with STT-MRAM, PCM (PRAM), ReRAM, and FeRAM as representatives. The new tier they form within the memory hierarchy — filling the performance gap between DRAM (volatile, fast) and NAND (non-volatile, slow) — is called Storage Class Memory (SCM).

The starting point for understanding emerging NVM is the fact that "today's memory hierarchy has a huge performance cliff." DRAM, close to the CPU, is fast with tens-of-ns latency but loses its contents when power is cut and is expensive; conversely, NAND-based SSDs are non-volatile, high-capacity, and cheap but have latency of tens of μs, hundreds to thousands of times that of DRAM. Between these lay an empty tier that would be "non-volatile yet nearly as fast as DRAM and directly byte-addressable." Emerging NVM aims to fill exactly this gap and thereby achieve a memory-storage convergence. The key point is that these do not replace DRAM or NAND outright, but rather find a unique place matched to each device's physical characteristics (speed, endurance, density, power) and thus subdivide the hierarchy.

B. Background and Necessity

Emerging NVM draws attention not from a mere desire for better performance, but from the structural backdrop that existing memory technologies have simultaneously hit physical and economic limits. The pressure can be examined along three axes.

The first axis is the scaling limit of DRAM. DRAM stores charge in a capacitor, and as the cell shrinks, charge leakage and refresh burden grow, so scaling has slowed sharply below the 10nm node. At the same time DRAM must refresh incessantly on a sub-μs cycle, consuming power even when idle. The second axis is the data explosion and AI workloads. Large language model training and inference, in-memory databases, and real-time analytics demand holding terabyte-scale data in memory, and the walls of capacity, cost, and power are too high to handle this with DRAM alone. The third axis is the limit of eFlash in the embedded domain. The eNOR flash once embedded in microcontrollers (MCUs) is hard to integrate below the 28nm node and is slow to write, reaching its limit as high-reliability embedded memory for automotive and IoT use.

Against this backdrop, the necessity of emerging NVM grew in two directions. One is large-capacity memory expansion for the datacenter (SCM), a path that uses non-volatility to retain data across reboots and to expand capacity more cheaply than DRAM. The other is embedded on-chip memory replacement (eMRAM, eReRAM), a path that pushes out eNOR flash in fine processes and provides faster writes, lower leakage, and higher reliability. Indeed, according to TechInsights' embedded and emerging memory roadmap, TSMC, GlobalFoundries, Samsung, UMC, Fujitsu, Sony, Renesas, and others are already mass-producing commercial STT-MRAM and ReRAM products on 20nm-class CMOS platforms, and TSMC and NXP have introduced 16nm FinFET-based automotive eMRAM. In short, emerging NVM is not a "laboratory device" but a technology already undergoing commercialization in specific niches.

C. Common Characteristics

Emerging NVMs differ in per-device principle but share several common characteristics. First, they store information in a physical state (resistance, magnetization, polarization) rather than in charge, so they are free from charge leakage and naturally gain non-volatility. Second, they allow byte-addressable access, so unlike NAND, which is handled only in block units, they can be read and written granularly like memory. Third, most are integrated in a 1T1R or crosspoint structure, leaving room to raise density above DRAM. Fourth, they commonly share write endurance and cell-to-cell uniformity as weaknesses, so a controller, ECC, and wear leveling to hide these are essential — requiring hardware-software co-design like an SSD.

2. The Memory Hierarchy and the Place of SCM

An old adage of memory design is "fast, large, or cheap — pick two of three." Why emerging NVM is needed becomes clearest when surveying the whole memory hierarchy. The traditional hierarchy runs register → cache (SRAM) → main memory (DRAM) → secondary storage (NAND SSD/HDD), and the performance-cost gap between DRAM and SSD reaches hundreds of times, so this span acts as the bottleneck of the whole system. SCM steps into exactly this gap and turns the hierarchy into a continuous ladder.

flowchart TB
  subgraph FAST["Fast · costly · small"]
    REG["Register (sub-ns)"]
    CACHE["Cache SRAM (~1-10ns)"]
    DRAM["Main DRAM (~10-100ns, volatile)"]
  end
  SCM["Storage Class Memory<br/>(Emerging NVM, ~100-500ns, non-volatile)"]
  subgraph SLOW["Slow · cheap · large"]
    NAND["NAND SSD (~10-100us)"]
    HDD["HDD/tape (~ms or more)"]
  end
  REG --> CACHE --> DRAM --> SCM --> NAND --> HDD
  style SCM fill:#e8f0fe,stroke:#2f6fed,stroke-width:2px
  style DRAM fill:#fef7e8,stroke:#e0a500,stroke-width:1px

In this hierarchy diagram, SCM's place is just below DRAM and just above NAND. It is slower than DRAM (on the order of hundreds of ns) but about 100 times faster than NAND, and the decisive differentiator is that its contents remain even when power is cut. For example, Intel Optane persistent memory had a measured read latency of about 100–300ns, positioned precisely between DRAM (tens of ns) and NAND SSD (tens of μs). This combination of "medium speed + non-volatility + byte-addressable access" enables new uses that no existing tier offered.

Here it is worth noting why byte-addressable access matters. A NAND SSD is a block device, so even to change the smallest datum it reads and writes in page/block units and must traverse the filesystem and block layers. SCM, by contrast, is accessed directly at a memory address by the CPU's load/store instructions like DRAM, so the overhead of the software stack (system calls, DMA, interrupts) disappears. This difference appears especially large for metadata, indexes, and logs that see many small, frequent updates, so the felt performance improvement differs even for the same media latency.

SCM is used in systems in two operating modes. The first is memory mode, which makes it appear to the OS as a huge volatile memory and uses DRAM as a cache to expand memory capacity cheaply. It is easy to adopt because large memory can be gained without application changes, but it does not use the benefit of non-volatility (persistence) and exposes SCM latency directly on a DRAM cache miss. The second is App-Direct mode, in which the application explicitly recognizes non-volatility and reads and writes persistent data directly in byte units. The latter can omit the step of a database flushing its log to disk and guarantee persistence with a memory write alone, dramatically reducing transaction latency.

However, App-Direct mode is not free. If power is cut while a write still resides in the CPU cache and has not yet reached SCM, the data is lost, so the application must explicitly persist writes and guarantee update ordering with instructions such as CLWB and SFENCE. It must also design, by itself, failure atomicity that prevents a "half-written (torn)" update, along with recovery logic. What hides this complexity are libraries such as PMDK and the filesystem's DAX mode, and the presence or absence of this software asset governs the success or failure of using SCM.

3. Emerging NVM Device Technologies

Understanding each device's operating principle reveals why each technology targets a different niche. The common architecture is a crosspoint or 1T1R structure that places a resistance-change element (or a magnetic element) at the intersection of a wordline and bitline and distinguishes 0 and 1 by the level of resistance. 1T1R places one select transistor and one resistive element per cell to suppress sneak-path interference among adjacent cells, giving high reliability, whereas crosspoint places an element only at intersections without a transistor to maximize density but must block leakage paths with a selector. Which structure is chosen determines the density-reliability trade-off.

flowchart LR
  subgraph CELL["Resistive cell structure (1T1R)"]
    WL["Wordline (select transistor)"] --> R["Variable resistance element"]
    R --> BL["Bitline (sensing)"]
  end
  R -.->|"MRAM"| M["Magnetization (MTJ parallel/antiparallel)"]
  R -.->|"PCM"| P["Crystalline/amorphous phase change (GST)"]
  R -.->|"ReRAM"| F["Oxygen-vacancy filament form/rupture"]
  R -.->|"FeRAM"| D["Ferroelectric polarization direction"]
  style CELL fill:#e8f0fe,stroke:#2f6fed,stroke-width:2px

A. STT-MRAM (Spin-Transfer Torque MRAM). It uses the property that, between the two magnetic layers of a magnetic tunnel junction (MTJ, Magnetic Tunnel Junction), resistance is low when the magnetization directions are parallel and high when antiparallel. The MTJ consists of a reference layer, an insulating tunnel barrier, and a free layer, and records 0 and 1 by changing only the free layer's magnetization. Whereas the older toggle MRAM flipped magnetization with an external magnetic field, which was unfavorable for power and integration density, STT-MRAM flips magnetization by torque, passing a spin-polarized current directly through the element, so the current path is confined within the cell, becoming favorable for scaling and low power.

Its greatest strengths are very fast writes (ns class) and effectively near-infinite endurance (10^12–10^15 cycles), plus non-destructive reads. This is because, unlike PCM, which needs physical heating on every write, or ReRAM, which forms a new filament, switching the magnetization direction does not wear out the element. However, the MTJ's resistance ratio (the resistance difference between parallel and antiparallel) is not large, so the sensing margin is narrow; the cell area is relatively large; and as scaling proceeds, securing thermal stability and reducing write current conflict in the effort to prevent thermally-induced bit flips.

Because of these traits, STT-MRAM first settled in as embedded memory (eMRAM) replacing SRAM caches or eNOR flash rather than large-capacity storage, and Samsung, TSMC, GF, UMC, and others are mass-producing it for automotive and IoT MCUs. For example, automotive electronic MCUs require decades of data retention and fast writes in harsh thermal environments, and eMRAM shows an advantage over eNOR flash in write speed and endurance, so leading-edge-process adoption is rising, as with TSMC/NXP's 16nm FinFET automotive eMRAM.

Another target STT-MRAM aims at is the non-volatilization of the last-level cache (LLC) and working memory. If the cache normally handled by SRAM is replaced with non-volatile MRAM, normally-off computing that preserves state even with power fully cut during idle becomes possible, greatly raising the energy efficiency of low-power devices that operate intermittently, such as wearables and sensor nodes. This also becomes a hardware foundation for the intermittent computing discussed earlier.

B. PCM/PRAM (Phase-Change Memory). It uses the principle that a chalcogenide material (typically GST, Ge-Sb-Te) switches between a crystalline (low-resistance) and amorphous (high-resistance) state by heat. Melting it with a short, strong pulse and quenching leaves the atoms disordered and frozen into an amorphous state (reset, high resistance), while slowly passing near the critical temperature with a weak pulse re-orders them regularly into a crystalline state (set, low resistance). The resistance difference is large, tens to hundreds of times, making sensing easy, and multi-level cell storage that divides the intermediate resistance into several steps is possible, raising density per bit.

Structurally it stacks well as crosspoint, which was favorable for high capacity, and Intel/Micron's 3D XPoint (Optane) was the representative commercialization case of this family. However, each write needs hundreds-of-°C heating for the phase change, so write power is large and endurance (about 10^6–10^9 cycles) falls short of DRAM/MRAM; managing the thermal crosstalk of heat spreading to adjacent cells and the resistance drift by which an amorphous state's resistance changes over time is tricky.

Intel formalized the wind-down of its Optane business in Q2 2022 and took an inventory impairment charge, and it folded the line in stages — the 100 series in 2023, the 200 series with final orders at the end of 2024 and shipments ending in 2025. This is assessed as a failure of the ecosystem rather than of the technology — a single company found it hard to single-handedly sustain an ecosystem of dedicated memory controllers, platform support, software (PMDK), and sufficient demand, and once Micron departed first in 2021, the supply economics collapsed.

The PCM family nonetheless retains value as a design archetype for large-capacity non-volatile memory, thanks to its inherent strengths of crosspoint high density and multi-level storage. Optane's business termination does not mean the discarding of the PCM principle, and within the CXL-based memory expansion scheme discussed later, demand for high-density non-volatile devices has room to re-emerge.

C. ReRAM/RRAM (Resistive RAM). When voltage is applied inside a metal oxide film (e.g., HfOx, TaOx), a conductive filament made of oxygen vacancies forms (set) and ruptures (reset), changing the resistance. To first use the device, it undergoes a forming process that creates the seed of the filament with a strong voltage, after which the filament is broken and reconnected at low voltage. The device structure is simple, favorable for scaling and 3D stacking, with low write power and fast speed as advantages.

Commercialization has also advanced: TSMC productized a 22nm embedded ReRAM (HfOx-based), Fujitsu a TaOx-based ReRAM, and embedded ReRAM cases for STMicroelectronics and others are reported. However, because filament formation and dissolution are probabilistic phenomena at the atomic scale, the resistance distribution scatters cell by cell, and characteristics change under repeated writes, so securing uniformity and reliability remains the core challenge.

Interestingly, this continuous, analog resistance characteristic is both a drawback and an opportunity. That the resistance value can be finely controlled in multiple steps is unfavorable for digital memory, but in neuromorphic and in-memory computing it is reinterpreted as a synaptic weight element, opening a path to perform multiply-accumulate in the analog domain on a resistor array. This flow of memory extending into a compute element makes ReRAM a technology beyond a mere storage device.

D. FeRAM (Ferroelectric RAM). It stores data by flipping the polarization direction of a ferroelectric with an electric field. An external voltage changes the polarization direction, and on reading it senses the charge difference depending on whether polarization reversed. Write power is extremely low, speed is fast, and endurance is high (10^12 cycles or more), so it has been used steadily in low-power IoT, smart cards, industrial instrumentation, RFID, and the like.

Traditional FeRAM was based on PZT-family capacitors, so its compatibility with fine CMOS processes was low and the cell area large, making high capacity hard. Recently, however, the discovery of HfO2-family ferroelectrics (FeFET, Ferroelectric FET) made it possible to share materials and processes with existing high-k gate processes, so its affinity with logic processes rose greatly and it is being revisited. Still, capacity remains at the several-Mb class, so its mainstay is a niche specialized in ultra-low-power and high-endurance rather than large-capacity main memory. The FeRAM case shows the archetype of semiconductor-memory innovation in which "an old technology is revived upon meeting new materials and processes."

Grouping the four devices along one axis reveals the big picture that they split into "MRAM/FeRAM strong in speed and endurance" and "PCM/ReRAM strong in density and integration." The former use a reversible physical state of magnetization or polarization, so they wear little and target caches and embedded memory, while the latter involve structural deformation of phase change or filaments, so they do wear but target high capacity through multi-level and 3D stacking. This dichotomy maps directly onto the two application branches of "embedded memory replacement vs. storage class memory."

The device characteristics are summarized as follows. The table is only an aid to comparison, and because the figures vary widely by process and generation, they should be read as relative tendencies.

Category STT-MRAM PCM/PRAM ReRAM FeRAM (ref.) DRAM (ref.) NAND
Storage principle Magnetization Phase change Oxygen-vacancy filament Ferroelectric polarization Charge (capacitor) Charge (floating gate)
Write speed Very fast (ns) Medium Fast Very fast Very fast Slow (μs)
Endurance (writes) ~10^12 or more ~10^6-10^9 ~10^6-10^12 ~10^12 or more Infinite ~10^3-10^5
Density/stackability Medium High (multi-level, 3D) High (3D) Low Medium Very high
Non-volatility O O O O X O
Main application Embedded (eMRAM) SCM Embedded, in-memory computing Ultra-low-power IoT Main memory Large-capacity storage

The key to read from the table is that "no single one is comprehensively superior." STT-MRAM excels in speed and endurance but is unfavorable for high capacity due to low density; PCM is high in density but lags in endurance and power; ReRAM has good integration but uniformity is a challenge; and FeRAM is ultra-low-power but small in capacity. That is, each device is optimal only on a specific axis, and that axis coincides exactly with the niche the device has settled into. For this reason, rather than expecting "a single winner (universal memory)," a multi-tier coexistence structure that uses different devices by purpose is the realistic outlook.

4. Comparison and Application Cases

The fundamental reason differences arise among devices lies in "what information is stored in." DRAM and NAND, which store it in charge, suffer worse leakage and reliability problems as scaling reduces the charge, whereas emerging NVMs, which store it in a physical state such as resistance, magnetization, or polarization, are free from charge leakage. For this reason emerging NVM naturally gains non-volatility in principle. Conversely, changing the physical state on every write takes energy (especially PCM's heating), and because the state transition is probabilistic (ReRAM's filament), securing uniformity and endurance becomes a common difficulty. That is, the trade-off that "non-volatility is gained for free, but write reliability is paid for dearly" is the essence of this device group.

The fork in application strategy also arises here. Datacenter SCM values high capacity and high density, so the PCM family was favorable, but due to ecosystem problems Optane withdrew, and that role is now shifting to CXL (Compute Express Link)-based memory expansion. Even Intel pointed to CXL as Optane's successor, because CXL lets memory be shared and pooled in byte units over the PCIe physical layer, so DRAM and NVM can be flexibly tiered without being tied to a specific novel device. By contrast, embedded on-chip memory values reliability, write speed, and fine-process integration over capacity, so MRAM and ReRAM are rapidly replacing eNOR flash. This asymmetry — that the same "emerging NVM" struggles in the datacenter but surges in embedded — shows that a technology's success or failure depends not on device performance alone but on application context and ecosystem.

Three concrete cases can be cited. First, Intel Optane (PCM/3D XPoint), launched in 2017, was used for scaling up and fast restart of in-memory DBs (SAP HANA and the like), but with Micron's 2021 departure and Intel's 2022 business termination it receded into history — a representative case showing that technical feasibility and business sustainability are separate. Second, TSMC/NXP's 16nm automotive eMRAM met the high-temperature endurance and fast writes that autonomous-driving and electronic MCUs require, enabling leading-edge-process integration that is hard with eNOR flash. Third, ReRAM's in-memory computing application performs analog multiply-accumulate (MAC) on a resistor-element array to reduce the data-movement bottleneck of AI inference, leading to research and prototypes and showing the direction of dissolving the boundary between memory and compute.

One common misconception must be guarded against when judging application: the expectation that "emerging NVM = a dream memory cheaper and faster than DRAM." In reality no device simultaneously surpasses DRAM and NAND on all axes of speed, density, endurance, power, and cost. For example, MRAM is fast and highly endurant but low in density and thus expensive, while PCM is high in density but unfavorable in endurance and power. Therefore the adoption decision should start not from "which is best" but from "which axis my workload is sensitive to," and the right approach is to quantify write frequency, capacity, power budget, and reliability requirements to choose the device and operating mode (memory mode vs. App-Direct).

Another comparison axis is the positioning of DRAM replacement or NAND replacement. If SCM is used to complement and expand DRAM, "large capacity and persistence even if a bit slower" becomes the value, while if it is used to complement NAND, "much lower latency even if a bit more expensive" becomes the value. The former's representative workloads are in-memory DBs, large caches, and KV stores; the latter's are metadata storage, journaling, and low-latency logs. Because the baseline of the economic evaluation changes depending on which neighboring tier even the same device targets, comparison must be done not by absolute performance but by "relative value versus the replacement target."

5. Deep Dive — Latest Trends and Expected Exam Directions

The recent landscape change surrounding emerging NVM can be summarized by the point that the change in the system frame that holds the device has become more important than the advance of the device itself.

The core of the recent flow is a shift from "single novel-device competition" to "tier and interconnect-centric." The lesson Optane's withdrawal left is that no matter how excellent a device is, it is hard to single-handedly sustain an ecosystem of dedicated controllers, software, and sufficient demand. As a result, industry attention moved from forcing a specific device into DRAM/NAND toward flexibly tiering and pooling heterogeneous memory over the open interconnect called CXL. CXL 3.x standardizes memory pooling and sharing, enabling memory disaggregation in which memory formerly fixed per server is shared by multiple nodes. Within this frame, emerging NVM has room to re-settle as a "non-volatile CXL memory device." JEDEC too has defined the interoperability of non-volatile memory modules through the NVDIMM-family standards.

The second flow is the steady expansion in embedded and edge. Unlike the datacenter, in the embedded domain eMRAM and eReRAM are quietly growing while actually pushing out eNOR flash, and AI and big-data demand is raising the need for low-leakage, high-density memory to replace SRAM caches and eDRAM. In particular, below the 10nm leading-edge node, eNOR flash integration is nearly impossible, so eMRAM reaps a structural benefit as an alternative for memory storing embedded code and parameters in MCUs and SoCs. The third flow is convergence with compute-in-memory (CIM), an attempt to use the analog resistance characteristics of ReRAM and PCM as synaptic elements of neuromorphic and in-memory computation to fundamentally ease the von Neumann bottleneck.

The fourth flow is the maturation of standardization and the software ecosystem. For applications to use non-volatile memory safely, a programming model that guarantees atomicity and recovery on power loss is needed, and assets accumulated in the Optane era, such as the PMDK (Persistent Memory Development Kit) and the filesystem's DAX (Direct Access) mode, can be inherited by CXL-based non-volatile memory even if a specific vendor's device disappears. In the end, the point that "the abstraction layer that handles non-volatility survives longer" than the hardware device is another lesson the Optane case left.

The message running through these flows is that the value of emerging NVM lies not in "a single device that replaces DRAM/NAND" but in "a component that reorganizes the memory hierarchy." In the past there was a dream of universal memory in which one device unified all memory, but the reality converged toward specialization in specific niches as each device's strengths are distinct. As a result the memory hierarchy is being subdivided rather than simplified, and what binds this subdivision to an operable level is an open interconnect like CXL and software abstraction.

From the professional engineer's viewpoint, the expected exam directions can be organized as follows. ① Explain the place of SCM in the memory hierarchy diagram and the necessity of its emergence, with a figure; ② compare the operating principles and characteristics of STT-MRAM, PCM, and ReRAM and discuss their application niches; ③ analyze the cause of Optane's withdrawal from technical and ecosystem perspectives and explain why CXL becomes its alternative; ④ present the architecture, software, and operational considerations when adopting emerging NVM — rather than short-answer, it is likely to be set as an essay weaving together principle + comparison + strategy like this.

6. Considerations and Implications

Emerging NVM is not a topic to end as a "new-technology introduction" in the professional engineer exam, but one that demands integrated judgment spanning the memory hierarchy, architecture, software, security, operations, and business viability. The implications are organized from the following five viewpoints.

First, device selection should be decided by "application context," not "performance." Emerging NVM is not an all-purpose substitute but has a clear niche for each. For datacenter capacity expansion, rather than betting on a specific novel device, it is safer to choose the open standard of CXL-based memory pooling to distribute vendor lock-in and ecosystem risk. Conversely, for embedded and automotive high-reliability on-chip memory, eMRAM and eReRAM, already mature in mass production, are the realistic choice.

Second, non-volatility is a double-edged sword that demands a shift in the software paradigm. To properly use byte-addressable persistent memory, the application must explicitly manage consistency on power loss (cache flush, failure atomicity, recovery logic). Because non-volatility instead creates the security risk that sensitive data physically remains even after power-off, memory encryption and secure-erase design are essential. To obtain the benefit of adoption, hardware replacement alone is not enough; hardware-software co-design that designs the DB, OS, and runtime together is the premise.

Third, operational design premised on endurance and reliability limits is needed. Because PCM and ReRAM cannot be overwritten infinitely like DRAM, write distribution (wear leveling), wear monitoring, and ECC must be provided at the controller level, and a strategy that distinguishes write-intensive from read-intensive workloads to place devices governs TCO. Because reliability figures vary widely by generation and process, measured validation through a PoC is recommended.

Fourth, adoption should be judged by converting "standard and ecosystem risk" into a price. As the Optane case shows, tying a mission-critical architecture to a single-vendor proprietary device makes the replacement cost enormous upon supply discontinuation. Therefore not only the performance gain but also supply continuity, a second source, standards compliance (JEDEC, CXL), and a migration path must be evaluated together, and designing dependence on software abstraction (PMDK, DAX, CXL.mem) so that the upper layers can be reused even if a specific device disappears is the core of risk mitigation.

Fifth, the mid-to-long-term outlook and related technologies must be seen together. In the short term embedded eMRAM is the most certain growth axis; in the mid term, with the maturation of the CXL ecosystem, non-volatile CXL memory is likely to refill the place of SCM. In the long term, ReRAM/PCM-based in-memory computing may emerge as a disruptive technology that eases the data-movement bottleneck of AI acceleration. Therefore the professional engineer must survey emerging NVM integrally within the big picture of a memory-storage-compute convergence together with DRAM, NAND, CXL, PIM, and neuromorphic.

References

In one line: Emerging non-volatile memories (STT-MRAM, PCM, ReRAM, FeRAM) aim for a non-volatile, byte-addressable tier (SCM) that fills the performance cliff between DRAM and NAND, and by storing information in a physical state rather than charge they gain non-volatility naturally but pay dearly for write reliability — in the datacenter they spread via CXL-based memory pooling after Optane's withdrawal, in embedded via eMRAM and eReRAM, each in its own niche, and the choice must be decided by application context and ecosystem, not device performance.