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#GAA#나노시트#FinFET#BSPDN#2nm공정
Last updated · 2026-10-10

GAA (Gate-All-Around) Transistors and Next-Generation Semiconductor Scaling

1. Overview

A. Definition

A GAA (Gate-All-Around) transistor is a field-effect transistor (FET) whose gate completely surrounds the current-carrying channel on all four sides (top, bottom, left, right) to control charge flow. Going beyond the FinFET, in which the channel is a single fin, it stacks several thin nanosheets and wraps the gate around each sheet — a next-generation device structure.

As semiconductor scaling entered the 3nm and 2nm class, the race to make transistors smaller shifted from simply "reducing line width" to "how perfectly the gate controls the channel." A transistor is a switch that turns the channel current on and off via the gate voltage, and as the channel shortens, the gate loses its grip on the channel and current escapes — worsening leakage. GAA tackles this head-on by wrapping the gate around the channel on every side to maximize electrostatic control. Samsung was the first in the world to begin mass production under the name MBCFET™ at its 3nm-class node (SF3) in 2022, and as TSMC (N2) and Intel (18A, RibbonFET) adopted it in earnest at the 2nm-class generation, GAA is becoming the de facto standard structure for leading-edge processes.

B. Background and Necessity

Three converging pressures made GAA inevitable. The first is the intensification of short-channel effects. When the channel length shrinks to a few nanometers, the electric fields of the source and drain penetrate to the center of the channel and neutralize the gate's control, increasing off-state leakage (current flowing even when the gate is off) and DIBL (Drain-Induced Barrier Lowering), in which the threshold voltage wavers. In a planar structure the gate controls the channel from only one side, so this limit became pronounced around 20nm.

The second is the saturation of the FinFET itself. The FinFET that Intel introduced at 22nm in 2011 stood the channel up so the gate could wrap three sides, extending the planar limit for more than a decade; but around 3nm the room to further raise fin height/width or add fins ran out. The third is the explosion of performance and power demands. To meet the compute density and power efficiency that AI, data centers, and mobile require, one must push more current at the same voltage while reducing leakage — impossible without a new structure that fundamentally raises channel control. These three pressures converged to push the GAA idea of "wrapping the gate fully around the channel" into mass production.

This topic frequently appears in the professional engineer exam within the flow of asking about "scaling strategies after the slowdown of Moore's Law." Past scaling relied on Dennard scaling, in which reducing line width improved performance, power, and area together; but when that law broke in the mid-2000s, leakage and heat became the bottleneck. Since then the semiconductor industry has redefined the essence of scaling through structure (FinFET, GAA), 3D stacking (chiplets, CFET), and interconnect innovation (BSPDN) rather than planar shrinking. GAA is the current protagonist of this "reinvention of scaling," and so it must be understood in the context of a paradigm shift in semiconductor technology, beyond single-device knowledge.

2. Evolution of Transistor Structure and GAA Operating Principles

The evolution of transistor structure can be summarized as the history of "how many sides the gate controls the channel from." The structure diagram below shows the expansion of the gate–channel contact surface from planar → FinFET → GAA.

flowchart LR
  A["Planar MOSFET<br/>(gate controls 1 side)"] --> B["FinFET<br/>(gate controls 3 sides, 3D fin)"]
  B --> C["GAA nanosheet<br/>(gate fully surrounds 4 sides)"]
  C --> D["Post-GAA: Forksheet / CFET<br/>(maximize stacking density)"]
  A -. "short-channel effects worsen" .-> B
  B -. "scaling saturates(3nm)" .-> C

A. Limits of the Planar MOSFET and Short-Channel Effects

The planar MOSFET was the basic semiconductor device for half a century. It places source and drain on the silicon surface, stacks a gate oxide and gate over the channel between them, and uses the gate voltage to form or block a conducting layer at the channel surface. The problem is that this structure controls the channel from only the top side. It sufficed when channels were long, but as scaling shortened the channel, current began to leak through the lower part of the channel the gate could not reach.

Specifically, when the channel length approaches the width of the source/drain depletion region, the drain voltage lowers the channel's potential barrier (DIBL), the threshold voltage drops, and a few nanoamperes of leakage flow even with the gate off. In a chip integrating billions of transistors this leakage accumulates as static power, worsening heat and battery drain. This is exactly why the planar structure effectively reached the end of its life below 20nm. It was a turning point that revealed "how many sides the gate grips the channel from" to be the essential constraint on scaling.

B. FinFET: The Arrival of the 3D Gate

The FinFET stands the channel up vertically like a fin and wraps the gate around both sidewalls and the top of that fin — a three-sided control structure. As the gate–channel contact surface widened, electrostatic control rose sharply, allowing a shorter channel at the same leakage. After Intel first commercialized it at 22nm in 2011, TSMC and Samsung adopted it from 16/14nm, and the FinFET sustained scaling for about ten years from 22nm to the start of 3nm.

The FinFET's key scaling levers were making fins taller and thinner and adjusting the fin count to set the drive current. But if a fin becomes too thin, quantum confinement and mobility degradation reduce performance, and raising the fin further increases the aspect ratio and undermines manufacturing stability. Moreover, because drive current could be tuned only in integer units of "fin count," design fine-tuning flexibility was poor. As these limits converged around 3nm, the transition to GAA — laying channels down, stacking them, and fully wrapping them with the gate — became unavoidable.

In addition, there was also a physical limit to reducing the spacing between fins (Fin Pitch). If fins are stood too densely, it becomes hard to fill the gate and insulator between them, and leakage and interference grow. This means the "stand up and wrap" approach reached saturation in terms of density, while the "lay down and stack" nanosheet opens structural room to pack more channel into the same footprint. In the end, the transition from FinFET to GAA was inevitable not only for performance (control) but also for density (integration).

C. GAA / Nanosheet: Fully Surrounding the Channel with the Gate

GAA stacks the channel as several horizontal thin plates (nanosheets) and has the gate material completely surround all four sides of each sheet. Because the gate wraps the channel on every side, electrostatic control is a step stronger than the FinFET's three-sided control, allowing a shorter channel at the same leakage level while suppressing threshold-voltage variation and DIBL. As a result it operates stably even at low voltage, improving power efficiency (performance/watt).

Another decisive advantage of the nanosheet structure is that channel width (Wsheet) can be tuned continuously. Unlike the FinFET, which could change drive current only in the discrete unit of fin count, the nanosheet can finely adjust current by widening or narrowing the sheet. Wide sheets go to high-performance, high-current cells and narrow sheets to low-power, high-density cells, so performance-power-area (PPA) can be flexibly optimized within the same process. Emphasizing this width-tunable nanosheet, Samsung calls its GAA the MBCFET (Multi-Bridge-Channel FET). However, the stacking process and the process of filling the gate between each sheet are far more complex than in a FinFET, so manufacturing difficulty and securing early yield remain the key challenges.

D. Electrostatic Control and Subthreshold Swing

The relative merits of the three structures ultimately converge on a single metric: how tightly the gate grips the channel. The subthreshold swing (SS), which indicates how steeply current drops in the turn-off region of the transistor, is theoretically limited to about 60mV/decade at room temperature; when gate control is weak this value grows (becomes shallower), worsening the on/off contrast for a given voltage change and increasing leakage. The more sides the gate wraps the channel — one side (planar) → three sides (FinFET) → four sides (GAA) — the closer SS approaches its theoretical limit, and the smaller DIBL and threshold-voltage variation become. This is why the "history of expanding the contact surface" is also the "history of improving power efficiency."

When the channel thins to a few nanometers, the quantum confinement effect makes carrier mobility and threshold voltage sensitive to thickness. Therefore, controlling the thickness and width of the nanosheet uniformly down to the atomic-layer level is key to reducing device-characteristic spread, and this ties directly to the yield and variability challenges discussed later. The table below summarizes the causes and implications of the differences among the three structures.

Category Planar MOSFET FinFET GAA Nanosheet
Gate control surface 1 side (top) 3 sides (fin sides/top) 4 sides (fully surrounded)
Representative nodes 20nm and above 16–3nm 3/2nm-class and below
Drive-current tuning channel width (W) continuous fin count (discrete) sheet width/stack count (quasi-continuous)
Short-channel control low (leakage worsens) medium high (SS/DIBL improved)

As the table shows, the core value of GAA is the combination of "control from full wrapping" and "the continuous design freedom of sheet width." Restoring the design flexibility that the FinFET had been bound to by the integer constraint of fin count is an important practical benefit in an era of scaling slowdown.

3. GAA Process/Manufacturing Architecture and Core Technologies

The difficulty of GAA lies not in the concept of the structure but in the manufacturing question of "how to fill the gate into the gaps between the stacked nanosheets." The process diagram below shows the representative manufacturing flow of the nanosheet GAA, together with the position of the two pillar technologies (backside power delivery, High-NA EUV) that underpin the 2nm generation.

flowchart TB
  S1["Si/SiGe superlattice stacking<br/>(alternating channel/sacrificial layers)"] --> S2["fin-shape etch<br/>(shape the whole stack into a fin)"]
  S2 --> S3["inner-spacer formation<br/>(gate isolation on source/drain side)"]
  S3 --> S4["channel release<br/>(selective removal of SiGe sacrificial layer)"]
  S4 --> S5["full gate wrap<br/>(High-k dielectric + metal gate)"]
  S5 --> S6["backside power delivery(BSPDN)<br/>(power network on wafer backside)"]
  subgraph Litho["Lithography axis"]
    L1["EUV(0.33 NA)"] --> L2["High-NA EUV(0.55 NA)"]
  end
  S2 -. "fine patterning" .-> Litho

A. Nanosheet Formation Process — Superlattice, Channel Release, Inner Spacer

The starting point of nanosheet GAA manufacturing is superlattice stacking. Silicon (Si, the layer that becomes the channel) and silicon-germanium (SiGe, the sacrificial layer to be removed later) are grown alternately at the atomic-layer level to build a multi-layer sandwich. After the whole stack is etched into a fin shape, the most delicate step, channel release, selectively dissolves only the SiGe sacrificial layer so the Si nanosheets remain suspended in air. The gate then fully surrounds each channel by seamlessly filling the fine gaps between the sheets with High-k dielectric and metal gate.

A decisive enabling technology in this process is the inner spacer. The gate must wrap the entire channel yet remain electrically separated from the source and drain, so an insulator is implanted in advance at the ends between the sheets to block parasitic capacitance and leakage between the gate and the source/drain. If the inner spacer is not uniform, device characteristics waver greatly, so the precision of atomic-layer deposition (ALD) and selective etch dictates yield. In short, GAA is a structure with more process steps and dramatically narrower tolerances per step than the FinFET, and this is the fundamental reason why securing early yield is difficult.

Interestingly, the GAA process is not a set of entirely new technologies but reuses a substantial portion of existing FinFET process assets. Superlattice stacking, HKMG, and EUV lithography are already mature technologies, and GAA's core new steps are effectively concentrated in "channel release and inter-sheet gate fill." For this reason, foundries design the transition from FinFET to GAA as a gradual evolution to spread process-development risk and investment burden. This is a classic engineering strategy of reducing transition cost by securing continuity with existing assets when adopting new technology, sharing the same spirit as the principle of gradual transition in architecture modernization or legacy migration.

B. Backside Power Delivery (BSPDN, Backside Power Delivery Network)

Another axis that characterizes the 2nm generation is BSPDN, which supplies power from the backside of the wafer. Traditionally, signal wiring and power wiring were both mixed in the multi-layer metal above (the front of) the transistor; as scaling crowded the wiring, power lines pushed out signal lines and the voltage drop (IR drop) worsened. BSPDN separates the power wiring to the backside of the wafer, concentrating the front side on signal wiring and supplying power directly through the thick backside metal. As a result it simultaneously gains reduced voltage drop, relieved wiring congestion, and smaller cell area.

Intel is known to have pre-emptively applied this under the name PowerVia at its 18A generation, putting it into mass production first in the industry; TSMC has disclosed a roadmap introducing it as the Super Power Rail in a subsequent generation (A16), and Samsung in a specific variant of the SF2 family. However, since each company's applied node and timing may be adjusted with each announcement, the latest disclosures should be checked. BSPDN is, combined with GAA, a key means of boosting 2nm-class power efficiency, but it adds a process of flipping the wafer, grinding it extremely thin, and forming wiring on the backside, bringing new challenges in heat-dissipation paths and manufacturing complexity.

From a manufacturing standpoint, BSPDN is implemented by bonding the wafer on which the transistors were built to a carrier, grinding the backside down to a thickness of a few micrometers, and drilling nano-TSVs (through-silicon vias) up to the power supply points on the front to connect to the backside power network. Power thus reaches the device directly through a short, thick path, reducing resistance and inductance, while the front metal layers are devoted entirely to signal wiring, improving routing congestion and cell area. On the other hand, since the device is sandwiched between thin silicon, heat dissipation worsens, and the stress/damage the backside process inflicts on the device must be suppressed, so BSPDN is a classic trade-off technology that exchanges power/area gains for heat/yield risk.

C. High-NA EUV Lithography

To print the fine patterns of the nanosheet, the resolution of the lithography equipment must keep up. Current leading-edge processes use EUV (extreme ultraviolet, wavelength 13.5nm, numerical aperture NA 0.33); going to the finer 1.4nm/1nm class increases the cost and error of multi-patterning, which overlays multiple exposures. The breakthrough for this is High-NA EUV, which raises the numerical aperture to 0.55, printing finer patterns in a single pass and reducing multi-patterning. The industry generally expects High-NA EUV to be deployed in earnest around the 1.4nm/1nm-class boundary; Samsung is known to consider adoption at the 1nm-class (SF1A) stage, and TSMC and Intel around the 1.4nm class, though the specific timing differs by company and is in flux. Because a single High-NA EUV tool costs on the order of hundreds of millions of dollars, the timing and scope of adoption is an area decided carefully by the balance of performance gain against investment recovery.

D. High-k Metal Gate and Strain/Channel Engineering

GAA performance also depends on the quality of the gate stack that wraps the channel. As the gate oxide thins, tunneling leakage grows, so an HKMG (High-k Metal Gate) is essential — a high-permittivity High-k dielectric (e.g., HfO₂-based) keeps the physical thickness while making it electrically thin, with a work-function-matched metal gate stacked on top. In GAA this stack must be filled conformally into the narrow gaps between sheets, so the uniformity of atomic-layer deposition (ALD) determines device characteristics.

In addition, strain engineering to raise carrier mobility and the choice of channel material are also important variables. Growing a material with a different lattice constant epitaxially at the source and drain to strain the channel increases the mobility of electrons and holes. In the long run, research is also underway to apply high-mobility channels such as germanium and III-V or 2D materials to the nanosheet, beyond silicon — showing that material innovation, not just structure (GAA), is another axis of scaling.

E. Process Variability and Yield Challenges

The essential reason GAA is harder than the FinFET lies in its increased process steps and reduced tolerances. If the spread grows in any of the completeness of the etch that selectively removes only SiGe at channel release, the uniformity of the inner spacer, or the conformality of the inter-sheet gate fill, the threshold voltage and leakage waver, increasing device-to-device variability. In fine devices, RDF (Random Dopant Fluctuation), in which the dopant count fluctuates statistically, and line-edge roughness (LER) pile on, so gathering the characteristics of billions of devices into a narrow range is yield itself. Reports of Samsung's early 3nm yield struggles are a clear case showing the difficulty of this variability control, demonstrating why early adoption of a new structure carries great risk.

4. Comparison of Foundry Implementations and Cases

GAA shares the same concept, but the implementation naming, adopted node, and combination of enabling technologies differ by company. The comparison below shows together the reasons the differences arise and their practical implications.

Category Samsung TSMC Intel
GAA name MBCFET (nanosheet) Nanosheet RibbonFET
First GAA mass production 3nm-class (SF3, 2022, industry first) from 2nm-class (N2) generation 18A (2nm-class) generation
Backside power delivery specific variant of SF2 family A16 (Super Power Rail) 18A (PowerVia, pre-emptive)
Strategic characteristic emphasizes width-tunable nanosheet, early transition stable transition centered on ecosystem/yield pursuit via simultaneous GAA+BSPDN

Samsung aimed to seize technological leadership by transitioning to GAA early at 3nm, a generation ahead of rivals, but is known to have struggled to stabilize early yield — symbolically illustrating the strategic trade-off of "advance the timing of the structural transition, or transition after yield has matured." TSMC, by contrast, took the conservative path of pushing the FinFET to 3nm and then transitioning to GAA at 2nm (N2), prioritizing ecosystem/yield stability. Intel aimed to catch the leaders with the aggressive strategy of applying GAA (RibbonFET) and BSPDN (PowerVia) simultaneously at 18A; putting two new technologies into one node at once is a choice that raises both the potential for a performance leap and the mass-production risk. As such, even the same GAA diverges greatly in yield, cost, and performance depending on the transition timing and the combination of enabling technologies.

In terms of concrete performance metrics, each company has presented figures to the effect that the GAA 2nm-class generation raises performance by about 10-odd % at the same power, or lowers power by around 20–30% at the same performance, and improves logic density by a certain margin versus the prior generation. For example, Samsung stated that its first-generation 3nm (SF3E) improves power efficiency, performance, and area versus the prior FinFET, and TSMC disclosed that N2 improves power, performance, and density versus N3. However, since these figures vary by comparison basis (same power vs. same performance) and target node and are updated at each announcement, it is safer to understand them as the trend of "double-digit-% power-efficiency improvement per generation" rather than quoting a specific figure definitively. The key is that such improvements no longer come from line-width shrinking alone as in the past, but from the combination of structure (GAA), power (BSPDN), and lithography (EUV).

As for actual application cases, mobile APs and AI accelerators are cited as the primary demand sources for GAA 2nm-class. Flagship mobile SoCs, where power efficiency ties directly to battery life, and data-center AI accelerators, where tens of thousands of chips run simultaneously and power/heat dominate total cost of ownership (TCO), are cases where tens of percent power savings per generation translate directly into operating-cost and carbon-emission reductions. This shows that the GAA transition is tied not to mere technological showmanship but to the power and cost competitiveness of the AI era.

From the perspective of the foundry competitive landscape, too, the GAA generation is an important inflection point. In the FinFET era, TSMC led the leading-edge foundry market with its yield/ecosystem advantage, but the GAA structural-transition period becomes both an opportunity for latecomers to catch the leader and a juncture for the leader to cement its dominance. Samsung's bringing out GAA first at 3nm, and Intel's attempt to counterattack by bundling GAA and BSPDN at 18A, are all strategic bets that treated this transition period as the decisive battlefield. However, since the final outcome is decided not by the order of structural adoption but by mass-production yield and customer acquisition, GAA competition can be called an arena where technological prowess and mass-production operational capability are contested together.

5. Deep Dive — Post-GAA (Forksheet/CFET) and the Latest Roadmap

GAA is not a terminus but the starting point of structural evolution that pushes stacking density even higher. The roadmaps of semiconductor research consortia such as imec draw the era after the GAA nanosheet as follows. First, the Forksheet reduces cell area by erecting a dielectric wall between the nFET and pFET to place the two devices closer together, and is presented as a bridge between the nanosheet and CFET. The next stage, the CFET (Complementary FET), stacks n-type and p-type transistors vertically rather than side by side to integrate twice the devices in the same area, and is cited as a strong candidate for sub-1nm (A-class) nodes.

The appeal of CFET is clear. Stacking n-type and p-type transistors vertically integrates twice the devices in the same planar area, enabling a "3D-ization of area" that raises density without further line-width shrinking. But the cost is also large. The process of stacking devices of different polarities in vertical alignment, the wiring that connects the upper and lower devices, and the heat problem in which the heat of stacked devices overlaps are all close to unsolved challenges. Before this abrupt leap, the Forksheet serves as an intermediate bridge that gradually raises density by narrowing device spacing with a dielectric wall, easing the process/design shock of going from nanosheet to CFET.

Public roadmaps generally place the Forksheet in a generation after 2nm and CFET in a sub-1nm generation around 2029–2033, but such schedules have tended to slip by about a generation in the past, so they are hard to take definitively. Samsung is reported to have, in a recent roadmap update, adjusted its 1.4nm-class (SF1.4) to 2029 and presented a direction of introducing High-NA EUV from the 1nm class (SF1A); TSMC too has disclosed a 1.4nm-class (A14) combining second-generation GAA and backside power delivery around 2028. Because each company's figures and years change at each announcement, official roadmaps should be checked. The key implication is that the axis of scaling competition has shifted from the line-width number to "the combination of structural innovation (GAA→Forksheet→CFET), interconnect/power innovation (BSPDN), and lithography innovation (High-NA EUV)."

This transition also has direct implications for domestic industry. Samsung and SK hynix compete on both leading-edge logic (foundry) and HBM/advanced packaging, so GAA/BSPDN mass-production capability and memory–logic heterogeneous-integration capability together determine national competitiveness. A view that sees the GAA transition not as an issue of the logic process alone but as a joint challenge for the entire memory/packaging/materials-components-equipment ecosystem is needed, and this is a useful perspective when connecting a single-device technology to its industrial/policy context in a professional-engineer answer.

6. Considerations and Implications

First, the strategic choice of structural-transition timing. A new structure such as GAA offers a performance/power leap, but early yield is low, so early transition means mass-production risk and delayed transition means loss of technological leadership. The contrast between Samsung's early 3nm transition and TSMC's conservative 2nm transition can be used, from the professional-engineer perspective, as a typical case of the universal decision problem of "balancing the timing of new-technology adoption against yield maturity."

Second, the importance of Design-Technology Co-Optimization (DTCO). The gains of the GAA generation — nanosheet width tuning, cell redesign due to BSPDN, standard-cell library reconstruction, and so on — are not fully realized by changing the process alone. DTCO (Design-Technology Co-Optimization) capability, in which device, cell, and design are optimized together, dictates the actual PPA gain, and this leads to a strategy of linkage with the design-IP and EDA ecosystems.

Third, strategic asset-ization from a supply-chain/sovereignty perspective. The extremely limited supply of High-NA EUV equipment (effectively an ASML monopoly) and the oligopoly of leading-edge foundries make the 2nm-class process a national and corporate security asset. It connects directly to discussions of semiconductor subsidies, localization, and alliance-based supply-chain realignment (digital sovereignty), and this is a management/policy-level consideration beyond a technical issue.

Fourth, new challenges of heat, power, and verification. BSPDN raises power efficiency, but wafer thinning changes the heat-dissipation path, making thermal design more difficult, and vertical stacking like CFET produces heat interference between upper and lower devices. Furthermore, 3D/stacked structures require power, signal, and thermal integrity to be verified together at the package/chiplet level, so linked design with the aforementioned chiplet/heterogeneous integration (2.5D/3D packaging) and HBM is essential. GAA must be understood not as a standalone technology but as one axis of a system-level transition in which packaging, memory, power, and lithography innovations are interlocked.

Fifth, cost/investment recovery and mass-production strategy. As nodes become more leading-edge, fab/equipment investment (especially High-NA EUV) and mask costs surge, making it economically irrational to put every product on the latest node. Therefore, a chiplet-style process split that puts only the compute block on the GAA leading-edge process and the rest on mature processes, or a conservative strategy of transitioning after yield matures, can be reasonable in terms of cost. Balancing a new technology's performance gain against investment recovery and risk is a management-decision problem beyond technology selection, and from the professional-engineer perspective it demands the capability to design a technology roadmap together with an investment portfolio.

References

In one line: GAA is a 2nm-class transistor structure in which the gate fully surrounds the nanosheet channel on all sides to suppress short-channel effects and raise power efficiency; combined with width-tunable nanosheets, backside power delivery (BSPDN), and High-NA EUV, it replaces the FinFET and forms the axis of scaling innovation that continues into the Forksheet and CFET.