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#EUV#리소그래피#High-NA#ASML#미세공정
Last updated · 2026-10-21

EUV (Extreme Ultraviolet) Lithography and Next-Generation Semiconductor Patterning

1. Overview

A. Definition

EUV (Extreme Ultraviolet) lithography is a patterning technology that uses extreme ultraviolet light with a wavelength of 13.5nm as its light source to print circuit patterns onto semiconductor wafers. It renders the few-nanometer fine patterns that deep ultraviolet (DUV, 193nm) lithography could not draw in a single pass as close to a Single Exposure as possible, serving as the core manufacturing technology that enables leading-edge processes below 7nm.

The essence of semiconductor manufacturing is "copying" a designed circuit drawing onto a wafer with light, and the minimum line width that can be drawn is fundamentally constrained by the wavelength of the light source. As the Rayleigh equation resolution = k₁ × λ / NA shows, the shorter the wavelength (λ) and the larger the numerical aperture (NA), the finer the pattern that can be drawn. Because DUV lithography remained at a 193nm wavelength, reducing line width required Multiple Patterning — splitting the same layer into several exposures — which exploded the number of process steps, masks, cost, and defect rates. EUV opened the path to drawing fine patterns in a single pass without multiple patterning by shortening the wavelength from 193nm to 13.5nm, roughly a 14-fold reduction. The Netherlands' ASML is effectively the sole commercial equipment supplier, and Samsung Electronics, TSMC, Intel, and SK hynix have adopted it in leading-edge logic and DRAM processes.

B. Background and Necessity

Three layers of pressure made EUV an inevitable requirement. The first is DUV multiple patterning reaching its limit. To realize fine patterns below 10nm with DUV, a single layer had to be split into two (LELE) or four (SAQP) exposures; as the number of splits grew, masks were added by the dozen and etch/deposition steps were inserted between each exposure, exponentially worsening Overlay error, cost, and turnaround time (TAT). The second is the industrial demand for sustaining Moore's Law. Meeting the transistor density demanded by AI, mobile, and data centers required continued line-width shrinkage, and the only economical means of achieving it was shortening the light-source wavelength.

The third is the failure of an intermediate wavelength (157nm, an EUV alternative). In the early 2000s the industry examined 157nm F₂ laser lithography as a next-generation candidate, but it was effectively abandoned due to defects and cost issues in the lens material (CaF₂), so resources ultimately concentrated on EUV with no alternative. However, 13.5nm is absorbed by nearly all materials, so lenses (transmissive optics) cannot be used and a vacuum is required, and securing a powerful light source was extremely difficult — commercialization alone took about 20 years. It finally established itself as a mass-production technology in 2019, when TSMC first applied EUV in volume at 7nm (N7+) and Samsung at 7nm (7LPP). Thus EUV is the product of a physical demand — "the wavelength must shrink for scaling to continue" — meshing with an engineering tenacity that broke through it over 20 years.

In the Professional Engineer exam this topic appears in the context of "fine-process technology for sustaining Moore's Law", "semiconductor supply-chain and equipment hegemony", and "manufacturing cost–yield trade-offs". Beyond merely memorizing equipment specs, one must be able to explain why it had to be 13.5nm, why the ASML monopoly arose, and what process and design changes the High-NA transition forces, from the perspective of a technology paradigm shift.

C. Key Characteristics

EUV lithography has four essential characteristics that distinguish it from prior patterning technologies. First, its ultra-short wavelength (13.5nm) dramatically reduces the wavelength term in the Rayleigh equation, boosting single-exposure resolution. Second, because 13.5nm is absorbed by all materials, it forces a full-path vacuum and reflective optics — a hardware architecture fundamentally different from DUV. Third, stochastic behavior arising from photon scarcity becomes the key variable for performance and yield, changing process control from "determinism" to "probability management." Fourth, it is an ecosystem-intensive technology in which light source, optics, mask, resist, metrology, and software must interlock as one body.

These four characteristics are entangled with one another. To gain the advantage of a short wavelength, it takes on the constraints of reflective optics and a vacuum; those constraints increase light loss and demand a high-power source; and fine patterns in turn produce stochastic defects that require compensation across the entire ecosystem, such as resist and computational lithography. Understanding EUV therefore means surveying not a single piece of equipment but this entire chain of mutual constraints.

2. Structure and Operating Principle of the EUV Patterning System

An EUV scanner is built as an optical chain: "generate light (source) → collect and illuminate (illumination optics) → reflect off the mask (reticle) → project a reduced image onto the wafer (projection optics)." The overall structure diagram below shows the path from photon generation to pattern formation on the wafer.

flowchart LR
  SRC["Source (LPP)<br/>tin droplets + CO2 laser"] --> COL["Collector mirror<br/>elliptical multilayer reflector"]
  COL --> ILL["Illumination optics<br/>(many multilayer mirrors)"]
  ILL --> MASK["Reflective mask (Reticle)<br/>Mo/Si multilayer + absorber"]
  MASK --> PO["Projection optics (POB)<br/>reduction projection 4x/8x"]
  PO --> WAFER["Wafer + resist<br/>(photochemical reaction → pattern)"]
  subgraph VAC["full-path vacuum + reflective optics"]
    COL
    ILL
    MASK
    PO
  end

A. Light Source: Tin (Sn) Plasma and the LPP Method

The hardest gateway in EUV technology was stably producing a sufficiently bright 13.5nm source. Commercial tools use the LPP (Laser-Produced Plasma) method. Tiny tin (Sn) droplets are injected into a vacuum chamber about 50,000 times per second, and a high-power CO₂ laser strikes them in two stages (a pre-pulse flattens the droplet, then the main pulse hits it) to form a highly ionized plasma at hundreds of thousands of degrees Celsius; this plasma emits extreme ultraviolet light in the 13.5nm band.

The problem is efficiency and power. Only a few percent of the incident laser energy is converted into EUV, so obtaining the several-hundred-watt source needed for mass production requires a tens-of-kilowatt CO₂ laser. Source power directly governs throughput (WPH), so ASML and its source subsidiary Cymer raised output above 250W to reach the level of processing more than 150–200 wafers per hour. Also, tin debris flung from the plasma contaminates the collector mirror and lowers its reflectivity, so debris mitigation — flushing debris away with a hydrogen gas flow — becomes a key variable for lifetime and availability. Thus the source is the heart that determines an EUV tool's performance, cost, and availability.

Another reason source technology is difficult is stability and reproducibility. Tens of thousands of droplets per second must be injected at precise positions and sizes, and the laser must precisely hit each one to emit uniform EUV pulses. If even a single shot's energy fluctuates, the line width of the pattern exposed at that instant changes, leading to Dose Variation that manifests as degraded critical-dimension uniformity (CDU). The source therefore controls pulse energy with real-time feedback, and this fine pulse-by-pulse control capability is a hidden competitive strength that governs mass-production yield. Besides LPP, discharge-produced plasma (DPP) and free-electron laser (FEL) sources were also researched, but all current commercial mass-production tools have converged on the LPP method.

B. Reflective Optics: Mirrors, Not Lenses

13.5nm extreme ultraviolet is absorbed by nearly all materials, including glass and air, so light cannot be gathered by passing it through lenses as in DUV. EUV tools therefore keep the entire path under vacuum and handle light only with reflective mirrors. The core is the molybdenum/silicon (Mo/Si) multilayer mirror, which stacks tens to hundreds of alternating Mo and Si thin films tuned to half of the 13.5nm wavelength so that Bragg Reflection constructively interferes only at a specific wavelength, raising reflectivity to roughly 70%.

However, nearly 30% of the light is lost per mirror, and with more than ten mirrors used in the illumination and projection optics, most of the light leaving the source is lost before reaching the wafer. This is the fundamental reason EUV demands enormous source power. Mirrors also require atomic-scale (tens of pm) surface flatness and figure precision, supplied by Germany's ZEISS with world-leading ultra-precision polishing. Because optics quality governs resolution, aberration, and uniformity, an EUV tool's competitiveness rests on the combination of two extreme technologies: the source and the optics.

This loss chain reveals a core constraint of EUV design. Passing through more than ten 70%-reflectivity mirrors drops the overall transmission to around a few percent, so optical design must solve the trade-off of "securing sufficient correction performance while minimizing the number of mirrors." This is also why High-NA had to redesign the mirror arrangement and the anamorphic structure, and the optics are not a mere component but the design axis that defines the entire tool's performance.

C. Reflective Mask (Reticle) and Absorber

In EUV the mask (reticle) is also reflective rather than transmissive. A Mo/Si multilayer is stacked on a low-thermal-expansion substrate to form a reflective surface, and an absorber (such as TaN) is left on top in the shape of the pattern to divide the light into absorbed and reflected. EUV incident on the mask is reflected from the multilayer, passes through the projection optics, and is transferred as a reduced image onto the wafer.

The reflective mask creates several challenges. The first is mask blank defects. The Mo/Si multilayer forming the reflective surface runs to tens of layers, and if even a single atomic-scale defect (phase defect) lies beneath or between layers, the reflected phase is distorted and the pattern is warped. Such defects are buried under the absorber and hard to repair afterward, so near-defect-free mask blank fabrication and compensation techniques that place patterns away from defect locations are both required. The second is the mask 3D effect. Light enters the mask obliquely (oblique incidence), and because of the absorber thickness, shadowing and phase errors arise that distort the pattern; to reduce this, research continues on thinner, higher-absorption novel absorber materials (such as high-refractive-index metals). The third is the Pellicle. A DUV mask uses a thin protective film (pellicle) to keep dust off the focal plane, but in EUV it was extremely hard to secure a pellicle material that transmits over 90% of 13.5nm while withstanding hundreds of watts of heat. Without a pellicle, even a single particle on the mask is repeatedly transferred to every chip, causing catastrophic yield loss, so development of high-transmission, high-heat-resistance pellicles (polycrystalline silicon, carbon nanotubes, etc.) continues.

Because the mask is used repeatedly throughout the process, its completeness determines the quality of every chip. The four elements — absorber, multilayer, pellicle, and defect inspection — must all interlock at extreme levels, and for this reason a single EUV mask costs several times more than a DUV one. Ultimately the mask, alongside the source and optics, is counted as the third bottleneck that governs yield and cost in the EUV ecosystem.

D. Exposure Method: Step-and-Scan and Alignment

An EUV tool does not expose the entire wafer at once. It uses the Step-and-Scan method, in which the mask pattern is projected as a reduced image onto one exposure Field of the wafer, then the wafer stage moves (Step) to the next position and exposes again, repeating the process. Here the mask and wafer stages are synchronized to scan at high speed in opposite directions, and the precision stage and interferometer technology that aligns the two stages' positions to sub-nanometer accuracy governs overlay precision.

An important concept here is Alignment and Overlay. Because a semiconductor is made by stacking dozens of layers, a new layer's pattern must overlap the already-made layer below with nanometer-scale accuracy. If inter-layer alignment error grows, vias become misaligned and opens/shorts occur, causing yield to plummet. The EUV tool therefore reads the wafer's reference marks and corrects position in real time, and once half-field and stitching are introduced in High-NA, managing alignment error at the stitched boundaries becomes even more demanding. In other words, "how precisely you overlap (overlay)" is as much a pillar of fine-process yield as "how small you draw (resolution)."

3. The EUV Patterning Process and Key Technical Challenges

EUV lithography is not the problem of a single tool but an ecosystem process in which source, optics, mask, resist, and metrology interlock. The detailed process diagram below shows the flow of patterning one layer with EUV and the key challenges arising at each step.

flowchart TD
  A["Resist coating<br/>(CAR or metal-oxide MOR)"] --> B["EUV exposure<br/>(reduced projection of mask pattern)"]
  B --> C["Post-exposure bake (PEB)<br/>+ Development"]
  C --> D["Metrology/inspection<br/>(CD, overlay, defects)"]
  D --> E["Etch/deposition<br/>(pattern transfer)"]
  B -. "Stochastic defects" .-> X["photon shot noise<br/>→ line breaks/bridges"]
  C -. "LER/LWR" .-> Y["line-width roughness<br/>→ device variation"]
  D -. "overlay error" .-> Z["inter-layer misalignment<br/>→ yield loss"]

A. Resist and Stochastic Defects

The most essential challenge of the EUV process is the Stochastic Defect. As patterns shrink to a few nanometers, the number of EUV photons involved in forming one pattern becomes statistically small, and because of the Shot Noise of where photons land, random defects occur in which some lines break (bridge defects) and some holes close. These defects remain probabilistically no matter how precisely the process is controlled, so they act as a fundamental barrier to line-width shrinkage.

The methods to reduce this conflict. Increasing the exposure dose raises the photon count and reduces stochastic defects, but throughput falls and cost rises. On the resist side, instead of the existing chemically amplified resist (CAR), the metal-oxide resist (MOR, e.g., tin-based EUV resist), which responds sensitively with fewer photons and has high etch resistance, has emerged as an alternative. That is, resist sensitivity, resolution, and line-width roughness (LWR) stand in a triangular conflict called the RLS trade-off (Resolution-LER-Sensitivity), and satisfying all three simultaneously is the central challenge of improving EUV yield.

Resist is also strategic in terms of materials and supply chain. High-performance EUV resists are oligopolized by a few global material firms, and novel materials such as metal-oxide resists excel at fine-pattern performance but leave challenges to overcome for mass-production adoption, such as metal contamination and etch-tool compatibility. Within Korea as well, localizing core materials such as EUV resist and pellicles is treated as a key to semiconductor competitiveness, which ties directly to the materials-parts-equipment in-sourcing strategy pursued since the 2019 materials export-control episode.

B. Line-Width Roughness (LER/LWR) and Metrology

The degree to which a pattern's edge is finely jagged rather than an ideal straight line is called LER (Line Edge Roughness), and the variation in the line width itself is called LWR (Line Width Roughness). When the line width is a few nanometers, even a few-percent roughness widens the variation in device characteristics (threshold voltage, leakage), degrading yield and performance uniformity. Roughness originates from the earlier stochastic photon distribution, resist molecule size, and the development process, so source, resist, and process must improve together.

Catching all these defects requires the backing of Metrology & Inspection. Measuring the dimensions (CD), inter-layer alignment (overlay), and fine defects of few-nanometer patterns requires e-beam and EUV-based metrology tools, which are a high-difficulty industry in their own right. Ultimately EUV is an ecosystem that includes not only "the technology to print well" but also "the technology to precisely measure and feed back what was printed," and metrology precision directly translates into mass-production yield.

C. Computational Lithography and Compensation (OPC/ILT)

Even when a pattern is projected optically as-is, the image formed on the wafer is distorted differently from the design drawing because of diffraction and the mask 3D effect. The technology that deliberately deforms the mask pattern (bias, adding assist features) to compensate for this is OPC (Optical Proximity Correction), and going further, optimizing the mask shape by inversely computing the desired wafer image is ILT (Inverse Lithography Technology). In EUV the compensation computation explodes because oblique incidence and stochastic defects must also be considered, so Computational Lithography leveraging GPUs and AI has become essential infrastructure.

This step matters because EUV's resolution limit is determined not by pure optics alone but by the collaboration of "optics + software compensation." That is, even for the same tool, the actual yield and minimum pattern vary with the quality of OPC/ILT and the accuracy of the process model. Recently, AI-based process control that predicts defects in advance and adjusts exposure conditions has been combined in, showing that lithography is shifting from "the physics of light" to a "data- and compute-intensive process."

D. Throughput, Availability, and Cost

A single EUV tool costs roughly 200 billion won for the 0.33 NA class and about 500 billion won (roughly USD 400 million) for High-NA, with megawatt-class power consumption. Therefore hourly throughput (WPH) and Availability are the decisive variables governing chip cost. Because source power determines throughput and debris contamination, optics lifetime, and mask defects determine availability, EUV operation is subject to comprehensive management that entails not only equipment physics but also predictive maintenance and process stabilization.

In concrete numbers, for a tool processing 150–200 wafers per hour at a 250W source, the output difference between 90% and 70% daily availability reaches thousands of wafers per month, so 1% of availability translates into hundreds of millions of won in cost. That is why Samsung and TSMC increase the number of EUV-applied layers in DRAM and logic processes while managing investment efficiency with a strategy of selectively applying it to critical layers with clear cost benefits. Samsung, for example, raised cell density by gradually increasing EUV-applied layers in 1a/1b-nanometer-class DRAM, while TSMC took an incremental approach, starting with a few layers at N7+ and expanding the EUV layer count moving to N5 and N3. This shows it is a matter of process economics — judging "where and how much to apply for maximum benefit versus cost" rather than "how fast the newest technology is fully adopted."

4. Comparison: Versus DUV, and 0.33 NA vs. High-NA

Understanding EUV's position requires comparison along two axes. The first is the comparison with DUV, showing why EUV replaces multiple patterning; the second is the comparison of 0.33 NA (current generation) with 0.55 NA High-NA (next generation), showing why the optics must change again.

Category DUV (ArF-i, 193nm) EUV 0.33 NA High-NA EUV 0.55 NA
Wavelength/NA 193nm / 1.35 (immersion) 13.5nm / 0.33 13.5nm / 0.55
Single-exposure resolution ~38nm pitch (needs multiple patterning) ~13nm line width ~8nm line width
Optics transmissive lens (immersion) reflective mirror reflective mirror (anamorphic)
Exposure field full field (26×33mm) full field half field (needs stitching)
Main application ~10nm class and non-critical layers 7–2nm logic, DRAM sub-2nm logic, next-gen DRAM

The numbers in this table are merely a supplementary summary; the key is "why" the differences arise. The transition from DUV to EUV is essentially replacing multiple patterning with single exposure through wavelength shortening. Drawing below 10nm with DUV requires SAQP, splitting one layer into four exposures, which explodes masks and process steps, whereas EUV draws it in one pass, greatly reducing process steps and overlay-error causes. However, because EUV tools, masks, and resists are expensive, in practice the economic optimum is to mix them — EUV only for the finest critical layers, DUV for the rest.

As a concrete case, when realizing a 10nm-class metal interconnect layer with DUV using SAQP (self-aligned quadruple patterning), making one layer repeats core formation, spacer deposition, and etch several times, increasing masks to 3–4 and process steps to dozens. Switching to EUV single exposure, by contrast, realizes the same pattern with one mask and one exposure, greatly reducing process steps and also eliminating the overlay-error factors that accumulated between each exposure and etch. In fact, TSMC applied EUV to only about four layers at N7+, yet that transition alone is known to have meaningfully lowered mask count and process complexity versus DUV multiple patterning. Thus EUV's value lies not only in "smaller" but also in "simpler," and simplification directly leads to improvements in overlay, defects, and turnaround time (TAT).

The transition from 0.33 NA to High-NA (0.55) raises resolution one more step by increasing the numerical aperture. However, raising NA enlarges the optics and shallows the depth of focus, and in particular ASML's High-NA adopts Anamorphic optics to suppress aberrations, reducing by 8x in one direction and 4x in the other. As a result the exposure field drawn at once shrinks to half the former size (half field), so large chips require Stitching — exposing twice and joining them. That is, High-NA gains the benefit of resolution while paying the costs of field reduction, design constraints, and surging tool price, and this trade-off is why TSMC is carefully weighing High-NA adoption.

5. Deep Dive: The High-NA EUV Transition and Latest Industry Trends

The frontier of EUV technology lies in the High-NA (0.55 NA) transition. Beyond the 0.33 NA generation (NXE·Twinscan NXE:3800E, etc.), ASML began shipping the High-NA EXE series (EXE:5000 → EXE:5200) from 2024. The EXE:5200B was announced as a commercial mass-production tool carrying 0.55 NA anamorphic optics and targeting about 175 wafers per hour (WPH) at a 50mJ/cm² dose with overlay accuracy at the 0.7nm level. This is an attempt to once again reduce multiple patterning to single exposure and simplify the process at the sub-2nm generation.

The adoption pattern splits distinctly by company. Intel is the most aggressive, being the first in the industry to bring in a commercial High-NA (EXE:5200B) and use it to develop its 14A (1.4nm-class) process, reportedly aiming for risk production in 2027 and mass production thereafter. Samsung Electronics reportedly received its first EXE:5200B in late 2025 and will bring in additional units in the first half of 2026 to apply to its 2nm foundry lines, and SK hynix also installed a tool at its DRAM fab in 2025 to explore High-NA application to next-generation DRAM. In contrast, TSMC is observed as possibly weathering the A14 generation for a considerable time with 0.33 NA EUV multi-patterning and deferring full-scale High-NA adoption to around 2030, representing a cautious stance that weighs resolution gains against cost and maturity. Also, Belgium's research institute imec is deploying research and verification infrastructure alongside, targeting process qualification in Q4 2026 with an EXE:5200-class tool (reportedly about USD 400 million each). (※ The specific timelines for Samsung and TSMC are based on secondhand reporting, so they must be confirmed against each company's official announcements.)

Meanwhile, EUV has emerged as a key technology not only in logic but also in memory (DRAM). DRAM faces fierce scaling competition to shrink cell area; Samsung Electronics introduced EUV into volume production starting with 1a-nanometer-class (4th-generation 10nm-class) DRAM to raise cell density and increased the applied layer count moving to the 1b/1c generations. SK hynix also applies EUV from the 1a-nanometer class and is expanding it to high-value products such as HBM DRAM. Unlike logic, which uses EUV on complex interconnect layers, DRAM's application pattern differs in that EUV's advantage is large for uniformly drawing the repetitive fine patterns of the cell array in a single exposure. This is a case showing that, beyond the notion that "EUV = logic only," EUV has established itself as a breakthrough for memory scaling as well.

From the Professional Engineer answer perspective, this trend carries three implications. First, EUV is not a single technology but a platform requiring reinvestment generation by generation (the 0.33 → 0.55 → next-gen Hyper-NA discussion). Second, the oligopoly of the supply chain — equipment monopoly (ASML), optics monopoly (ZEISS), resist, pellicle, and so on — combines with geopolitical risk. Third, the half-field, stitching, and new resists that High-NA demands force a chain of changes reaching into design (EDA), masks, and materials.

6. Considerations and Implications

First, the application strategy is "selective application," not "EUV everywhere." EUV reduces multiple patterning and simplifies the process, but tool, mask, and resist costs are high, so using it on every layer is uneconomical. The standard is a hybrid that single-exposes only the finest critical layers with EUV and handles non-critical layers with DUV, and a Professional Engineer must be able to explain "which layer and why EUV is used" as a cost–yield–performance trade-off.

Second, supply-chain concentration is both opportunity and risk. EUV tools from ASML, optics from ZEISS, and the source from Cymer make the supply chain extremely concentrated, so export controls and geopolitical conflict directly connect to manufacturing capability. At the national and corporate level, localizing materials-parts-equipment, in-sourcing pellicles and resist, and securing multiple suppliers become strategic tasks, and this must be treated not as mere technology but as a matter of industrial security.

Third, stochastic defects are a fundamental scaling limit to be managed. The smaller the line width, the more unavoidable shot-noise-based stochastic defects become, so a combined strategy is needed to lower the probability through dose increase (sacrificing throughput), metal-oxide resist, and AI-based defect prediction/compensation (computational lithography, OPC/ILT). Yield is redefined as a matter of "probability management," not "perfect control."

Fourth, EUV must be understood in connection with other scaling technologies. Because lithography alone cannot achieve all of performance, power, and area (PPA), EUV sustains scaling at the system level by combining with GAA transistors, backside power delivery (BSPDN), chiplets/3D stacking, and computational lithography. A Professional Engineer answer must place EUV not as an isolated tool but as one axis of the next-generation semiconductor roadmap, with the depth to survey outlook (Hyper-NA, novel-material sources, etc.) and linked technologies.

Fifth, the outlook is "a gradual saturation of optical scaling" and "a shift of weight toward system scaling." After High-NA (0.55), Hyper-NA (around 0.75) optics are discussed, but the larger the NA, the steeper the field reduction, tool price, and design constraints become, making the economic limit evident. Therefore the central axis of scaling is expected to shift gradually from exposure resolution alone to system scaling such as 3D stacking (CFET, hybrid bonding), chiplets, and heterogeneous integration. A Professional Engineer must evaluate EUV in a balanced way as "a technology that shares roles with other innovations within physical and economic limits" rather than "a tool of endless line-width competition," and at the national-strategy level should approach it as a semiconductor ecosystem capability encompassing equipment, materials, metrology, and talent.

References

In one line: EUV lithography is a core manufacturing technology that replaces multiple patterning with single exposure using 13.5nm extreme ultraviolet, a tin-plasma source, and reflective (Mo/Si) optics to enable sub-7nm fine processes, and it is evolving toward High-NA (0.55 NA) while managing stochastic defects, cost, and supply-chain concentration.